Researchers from Peking University and the Shanghai Institute of Microsystem and Information Technology at the Chinese Academy of Sciences h...
Researchers from Peking University and the Shanghai Institute of Microsystem and Information Technology at the Chinese Academy of Sciences have developed a neural dynamical system chip based on phase-change memristors.
The work, published in Science under the title “A sub–10-millisecond neural dynamical system based on phase-change memristors,” introduces a controllable in-memory computing approach that combines device physics with neural dynamical algorithms.
The prototype reduces the latency of one neural dynamical system iteration to 2.12 milliseconds. In reported experiments, it also delivered substantial speed and energy-efficiency gains over existing dedicated accelerators, while supporting high-fidelity cortical surface reconstruction and three-dimensional manifold mesh generation.
Neural dynamical systems combine the expressive power of neural networks with the continuous evolution mechanisms of differential equations.
This makes them useful for tasks that require a model to represent how a physical system changes over time, including:
However, these systems are computationally demanding. Solving a neural dynamical model usually requires repeated numerical integration, error estimation, and adaptive step-size searches. Each iteration may involve several neural-network evaluations and repeated movement of intermediate data between memory and processing units.
On a traditional von Neumann architecture, storage and computation are physically separated. Data must travel between memory, caches, and arithmetic units throughout the calculation. The movement itself consumes time and energy, sometimes becoming more expensive than the mathematical operation.
For roughly half a century, the central challenge has been difficult to escape: how can a neural dynamical system preserve accurate continuous modeling while operating with low enough latency for real-time use?
The research team addressed the problem by using two programmable properties of phase-change memory devices:
Rather than treating these physical effects only as imperfections to be corrected, the researchers mapped them directly to useful computational operations.
The conductance drift is used for an in-situ adaptive integration step-size search. The multilevel conductance states are used for multiply-accumulate operations inside the memory array.
This creates a controllable in-memory computing system in which important parts of the neural dynamical algorithm are executed through the device’s own physical behavior.
A numerical solver does not always use the same time step.
When the modeled system changes slowly, a larger step may be accurate enough and can reduce the number of calculations. When the system changes rapidly, a smaller step is needed to control error.
Traditional hardware repeatedly calculates, compares, and adjusts this step size through digital logic. The new system instead encodes effective integration steps into the conductance states of phase-change devices and uses their controlled physical evolution during the search process.
The result is not simply memory placed closer to the processor. The memory device participates directly in the algorithm.
The embedded neural network still needs to store weights and perform matrix operations.
The team used accurately programmed multilevel conductance states to represent those weights inside a dense phase-change memory array. Matrix-vector multiplication can then be performed directly in the array rather than repeatedly loading values into separate digital multipliers and adders.
Combining adaptive step-size search and neural-network inference in the same physical system reduces:
This device–algorithm–architecture co-design is the main reason the chip can reduce latency while maintaining modeling accuracy.
The neural dynamical system chip was fabricated using a 40 nm process.
The in-memory computing and step-size drift arrays occupy a combined area of only 0.28 mm². The design also includes supporting circuits such as programming-pulse generators, analog-to-digital converters, drivers, and other peripheral logic.
The chip runs at 50 MHz. A single integration step uses a nine-stage pipeline and reaches a measured iteration latency of 2.12 ms.
| Specification | Reported Value |
|---|---|
| Fabrication process | 40 nm CMOS |
| Combined ENN-CIM and step-size drift array area | 0.28 mm² |
| Phase-change memory array | 147K 1T1R cells |
| Operating frequency | 50 MHz |
| Integration pipeline | 9 stages |
| Single-iteration latency | 2.12 ms |
| SET/RESET endurance | 10¹⁰ cycles |
| Reported yield | Above 99.9999% |
The paper describes the system as a sub–10-millisecond neural dynamical platform, while the measured single-iteration result highlighted in the report is 2.12 ms.
The research team compared the system with advanced dedicated neural dynamical system hardware and with an NVIDIA A100 GPU in high-fidelity modeling tasks.
For the same class of neural dynamical computations, the chip reportedly achieved:
| Comparison | Reported Result |
|---|---|
| Speed vs. dedicated NDS ASICs | 3.82×–36.27× faster |
| Power vs. dedicated NDS ASICs | 11.75×–24.73× lower |
| Speed vs. NVIDIA A100 in cortical modeling | 50.38×–478.18× faster |
These figures are task- and system-specific. They should not be interpreted as a claim that the prototype is universally faster than an A100 across general AI workloads.
The accelerator is designed for a particular neural dynamical computation pattern. Its advantage comes from mapping that workload tightly to phase-change device behavior and eliminating much of the data movement required by general-purpose digital hardware.
The team used the chip to reconstruct white-matter and gray-matter cortical surfaces and to generate three-dimensional manifold meshes.
The system starts from a closed genus-zero template and evolves it through a neural dynamical process toward the target brain structure. The integration path must remain smooth while preserving the topology of the surface.
The reported results show that the generated cortical surfaces were:
The reconstructions also performed well on geometric evaluation metrics such as:
These metrics measure how closely the reconstructed surface matches the reference structure, including both average deviation and more extreme boundary errors.
A brain-surface model is not useful simply because it looks visually similar to a brain.
It also needs a valid geometric structure. Self-intersections, holes, and non-manifold regions can make downstream analysis unreliable. They may affect anatomical measurements, navigation, simulation, and comparisons across time or between patients.
The neural dynamical approach continuously deforms a valid template toward the target. When the evolution is well controlled, it can preserve the topology of the original surface while adapting to complex anatomy.
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Future brain–computer interfaces will need to do more than recognize a signal and trigger a command.
Advanced systems may need to:
This process is highly sensitive to latency. A brain-state model that requires long offline processing cannot provide truly responsive interaction.
Millisecond-scale neural dynamical computing could support more individualized and continuously updated representations of neural state. That may eventually help brain–computer interfaces move from basic signal classification toward real-time modeling and adaptive interaction.
The current work is a research prototype, not a finished implantable BCI processor. Additional development would be required in integration, robustness, medical validation, packaging, data acquisition, and regulatory approval.
The research also suggests potential applications in medical imaging and computational neuroscience.
Possible future directions include:
For conditions such as Alzheimer’s disease and Parkinson’s disease, subtle changes in brain structure and function may be clinically meaningful. Faster modeling could eventually help researchers or clinicians analyze those changes more interactively.
However, the chip does not itself diagnose disease. Any clinical use would require validated medical models, representative datasets, prospective studies, system-level safety testing, and appropriate regulatory review.
A Science Perspective published alongside the paper described the work as part of a shift toward computing with device physics.
Conventional digital design often tries to suppress analog behavior, variation, and device drift. This project takes a different approach. It identifies physical device characteristics that can represent parts of the target algorithm and then builds the computing system around them.
This approach is especially relevant in the post-Moore era, where conventional transistor scaling alone can no longer deliver the same improvements in cost, energy, and performance.
Instead of relying only on smaller transistors, new systems increasingly combine:
The phase-change memristor chip is one example of that broader direction.
The project was led by teams including Professor Yuchao Yang of Peking University and Researcher Zhitang Song of the Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences.
The Science paper lists Lei Cai as first author. The official report also identifies Yaoyu Tao, Chenchen Xie, Longhao Yan, Yixin Zhu, and other collaborators involved in the research.
The work received support from programs and organizations including:
The paper was published in Science, Volume 393, Issue 6806, pages 105–112, with DOI 10.1126/science.aee6277.
The results are important, but several boundaries should remain clear.
The chip is optimized for a neural dynamical system workload. It should not be compared with a GPU as though both were general-purpose replacements for each other.
The paper demonstrates a fabricated and experimentally tested system. Manufacturing scale, long-term field reliability, packaging cost, software tooling, and production deployment remain separate engineering challenges.
Brain reconstruction is a meaningful demonstration, but clinical diagnosis or intervention requires a much larger body of medical evidence.
Phase-change devices can show variation, drift, nonlinearity, and environmental sensitivity. The significance of this research is that it controls and uses some of those behaviors, not that all analog-hardware challenges have disappeared.
A neural dynamical system combines a neural network with continuous-time differential equations. It can model how a physical or biological state evolves instead of producing only a static prediction.
A phase-change memristive device stores information through controllable material states that produce different electrical conductance levels. Its conductance can be programmed, retained, and used directly in memory-based computation.
It means the memory device performs useful parts of the calculation while storing data. In this chip, controlled conductance drift supports adaptive step-size search, while multilevel conductance supports neural-network multiply-accumulate operations.
The reported prototype completes one neural dynamical system iteration in 2.12 ms. The paper describes the full platform as a sub–10-millisecond system.
For the cortical surface reconstruction workloads tested by the researchers, the system was reported to be 50.38× to 478.18× faster. This is a specialized workload comparison, not a claim of higher general-purpose AI performance.
The neural dynamical chip was fabricated using a 40 nm CMOS process. Its in-memory computing and step-size drift arrays occupy a combined area of 0.28 mm².
Not as a finished clinical product. The research provides a possible hardware foundation for future real-time brain-state modeling, but practical BCI use would require further system integration, validation, and regulatory work.
The paper was published in Science under the title “A sub–10-millisecond neural dynamical system based on phase-change memristors.” Its DOI is 10.1126/science.aee6277.
Researchers from Peking University and the Chinese Academy of Sciences built a neural dynamical system chip that uses phase-change memristors for controllable in-memory computing. The device maps conductance drift to adaptive integration step-size search and multilevel conductance to neural-network computation.
The 40 nm prototype reaches 2.12 ms per iteration and reports substantial speed and power advantages over existing dedicated accelerators. In cortical surface reconstruction tasks, it also produced smooth, closed, topologically consistent brain models at much lower latency than the tested GPU implementation.
The chip is still a specialized research prototype, and its medical and brain–computer interface applications remain prospective. Even so, the work demonstrates how emerging memory physics can be used as an active computing resource rather than treated only as a storage mechanism.
The central breakthrough is not simply a faster chip—it is a device–algorithm co-design that turns phase-change memory behavior into part of the neural dynamical computation itself.
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